The present invention relates to a DLL (Delay-Locked Loop) circuit and, more particularly, to a digital DLL circuit for generating a clock having an arbitrary phase by controlling the phase of a predetermined external clock on the basis of a digital amount.
There is proposed a conventional digital DLL circuit for generating a clock having an arbitrary clock and the same frequency as that of an external clock by controlling the phase of the external clock on the basis of a digital amount. The arrangement of this conventional digital DLL circuit is shown in FIG. 8.
Referring to FIG. 8, a frequency divider 1 frequency-divides an external clock 11 into four clocks 12 made up of clocks I, Q, IB, and QB having a phase shift of 90.degree., and the four clocks 12 are output to a clock mixer 2. The clocks IB and QB are inverted clocks (phase difference of 180.degree.) of the clocks I and Q, respectively.
The clock mixer 2 mixes the clocks 12 on the basis of an output from a digital phase amount output circuit 5 to generate an internal clock 13 having a predetermined phase different from the external clock 11. In this case, a clock selection signal 17 (upper two bits) of an output from the digital phase amount output circuit 5 is used to select two clocks 12 to be mixed, and a phase signal 18 (remaining six bits) is used to designate the phase control amount (delay amount) of the internal clock 13 between the two selected clocks 12.
For example, while the clocks I and Q are selected by the clock selection signal 17, when the phase signal is given as "20H" (H represents that "20" is a hexadecimal number), the middle phase (45.degree. delayed phase) between the clocks I and Q is selected.
The internal clock 13 generated as described above is input to a subsequent system and a dummy delay circuit 3. The dummy delay circuit 3 adds to the internal clock 13 a desired delay amount equivalent to the line length up to the subsequent system, and outputs the sum as a delayed clock 14 to a phase determination circuit 4. The phase determination circuit 4 compares the phase of the external clock 11 with the delayed clock 14 from the dummy delay circuit 3 using a reference voltage 15 (Vref) as a threshold value. The phase determination circuit 4 outputs a phase determination signal 16 to the digital phase amount output circuit 5.
On the basis of the phase determination signal 16, the digital phase amount output circuit 5 generates the clock selection signal 17 and phase signal 18 made up of digital amounts output to the clock mixer 2. When the phase determination signal 16 is at H (High) level (FIG. 10A), the clock selection signal 17 and phase signal 18 output from the digital phase amount output circuit 5 are counted as a continuous 8-bit counter output, as shown in FIGS. 10B and 10C.
When the phase determination signal 16 changes to L (Low) level (FIG. 10D), the clock selection signal 17 and phase signal 18 are counted down as a continuous 8-bit counter output, as shown in FIGS. 10E and 10F.
As shown in FIG. 11A, while the DLL is locked, the phase of the delayed clock 14 from the dummy delay circuit 3 is locked with that of the external clock 11, and the phase determination signal 16 repeats H and L levels. As shown in FIGS. 11B and 11C, the clock selection signal 17 and phase signal 18 become almost stable, and the internal clock 13 having a desired phase (delay amount) can be obtained.
In the conventional digital DLL circuit, the loads of buffers and the size of the buffers in the dummy delay circuit 3 are adjusted to select an appropriate delay amount, as shown in FIG. 12, thereby controlling a phase position where the DLL is locked. An increase in delay amount has a limitation due to degradation of the waveform of the delayed clock 14, and an arbitrary phase cannot be set in a wide range. Therefore, the internal clock 13 having a large delay amount with respect to the external clock 11 cannot be obtained, resulting in inconvenience.